Publications

Journal papers

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

  A. Nomura, Y. Matsushita, J. Kadomoto, H. Matsutani, T. Kuroda, H. Amano
  International Journal of Networking and Computing (IJNC), vol. 8, no. 1, pp. 124–139, Jan. 2018.

Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO

  J. Kadomoto, S. Hasegawa, Y. Kiuchi, A. Kosuge, T. Kuroda
  IEICE Transactions on Electronics, vol. E99-C, no. 6, pp. 659–662, June 2016.

A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver

  A. Kosuge, J. Kadomoto, T. Kuroda
  IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 6, pp. 1446–1456, June 2016.

A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel

  L. Hsu, J. Kadomoto, S. Hasegawa, A. Kosuge, Y. Take, T. Kuroda
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E98-A, no. 12, pp. 2584–2591, Nov. 2015.

Conference papers

Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface

  J. Kadomoto, H. Irie, S. Sakai
  IEEE International Conference on Computer Design (ICCD), pp. 589–596, Oct. 2020.

Inductive-Coupling Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers

  J. Kadomoto
  International Symposium on Microelectronics (IMAPS), pp. 1–1, Oct. 2020.

A High-Performance Out-of-Order Soft Processor Without Register Renaming

  S. Mitsuno, J. Kadomoto, T. Koizumi, R. Shioya, H. Irie, S. Sakai
  International Conference on Field-Programmable Logic and Applications (FPL), pp. 73–78, Aug. 2020.

A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces

  J. Kadomoto, H. Irie, S. Sakai
  Asian CHI Symposium (AsianCHI), pp. 1–4, Apr. 2020.

A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers

  J. Kadomoto, H. Irie, S. Sakai
  IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), pp. 442–444, Apr. 2020.

An Inductively Coupled Wireless Bus for Chiplet-Based Systems

  J. Kadomoto, S. Mitsuno, H. Irie, S. Sakai
  Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 9–10, Jan. 2020.

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor

  S. Mashimo, A. Fujita, R. Matsuo, S. Akaki, A. Fukuda, T. Koizumi, J. Kadomoto, H. Irie, M. Goshima, K. Inoue, R. Shioya
  International Conference on Field Programmable Technology (FPT), pp. 63–71, Dec. 2019.

WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers

  J. Kadomoto, H. Irie, S. Sakai
  IEEE International Conference on Computer Design (ICCD), pp. 100–108, Nov. 2019.

An Inductively Coupled Wireless Bus for Inter-Chiplet Communication

  J. Kadomoto, H. Irie, S. Sakai
  International Conference on Solid State Devices and Materials (SSDM), pp. 1049–1050, Sep. 2019.

A Sensing Technique for Data Glove Using Conductive Fiber

  R. Takada, J. Kadomoto, B. Shizuki
  ACM Conference on Human Factors in Computing Systems (CHI), pp. INT023:1–INT023:4, May 2019.

A Sensing Technique for Data Glove Using Conductive Fiber

  R. Takada, J. Kadomoto, B. Shizuki
  Asian CHI Symposium (AsianCHI), pp. 1–5, May 2019.

An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming

  J. Kadomoto, T. Koizumi, A. Fukuda, R. Matsuo, S. Mashimo, A. Fujita, R. Shioya, H. Irie, S. Sakai
  International Conference on Field Programmable Technology (FPT), pp. 377–380, Dec. 2018.

QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS

  K. Ueyoshi, K. Ando, K. Hirose, S. Takamaeda-Yamazaki, J. Kadomoto, T. Miyata, M. Hamada, T. Kuroda, M. Motomura
  IEEE International Solid-State Circuits Conference (ISSCC), pp. 216–217, Feb. 2018.

A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface

  A. Nomura, J. Kadomoto, T. Kuroda, H. Amano
  International Symposium on Computing and Networking (CANDAR), pp. 126–131, Nov. 2017.

An Inductive-Coupling Link for 3-D Network-on-Chips

  J. Kadomoto, H. Amano, T. Kuroda
  International SoC Design Conference (ISOCC), pp. 150–151, Nov. 2017.

Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface

  A. Nomura, H. Matsutani, T. Kuroda, J. Kadomoto, Y. Matsushita, H. Amano
  International Symposium on Computing and Networking (CANDAR), pp. 195–201, Nov. 2016.

An Inductive-Coupling Bus with Collision Detection Scheme Using Magnetic Field Variation for 3-D Network-on-Chips

  J. Kadomoto, T. Miyata, H. Amano, T. Kuroda
  IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 41–44, Nov. 2016.

A 1 Tb/s/mm² Inductive-Coupling Side-by-Side Chip Link

  S. Hasegawa, J. Kadomoto, A. Kosuge, T. Kuroda
  European Solid-State Circuits Conference (ESSCIRC), pp. 469–472, Sep. 2016.

Analytical ThruChip Inductive Coupling Channel Design Optimization

  L. Hsu, J. Kadomoto, S. Hasegawa, A. Kosuge, T. Kuroda
  Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 731–736, Jan. 2016.

3D Integration Using Inductive Coupling and Coupled Resonator (Invited)

  Y. Take, J. Kadomoto, T. Kuroda
  IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), pp. 46–48, Aug. 2015.

A 6Gb/s 6pJ/b 5mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and EMC-Qualified Pulse Transceiver

  A. Kosuge, S. Ishizuka, J. Kadomoto, T. Kuroda
  IEEE International Solid-State Circuits Conference (ISSCC), pp. 176–177, Feb. 2015.

Design and Analysis for ThruChip Design for Manufacturing (DFM)

  L. Hsu, Y. Take, A. Kosuge, S. Hasegawa, J. Kadomoto, T. Kuroda
  Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 46–47, Jan. 2015.

© 2021 Junichiro Kadomoto.